1. Field of the Invention
The present invention relates to a tester used for testing a semiconductor circuit device. During testing, the tester inputs a test pattern to the semiconductor circuit device and determines whether or not the semiconductor circuit device is good or bad based on a result as to how the semiconductor circuit device responds to the input test pattern.
In particular, the present invention relates to a test-vector editing system and method for generating and editing test vectors which are used for performing a static supply (electric) current (I.sub.DDQ) test of a CMOS circuit.
2. Description of Related Art
Recently, with progress of miniaturization and circuit density improvement of semiconductor integrated circuits, various new defect modes have been appearing which could not be detected through conventional testing methods. Such defects could not be detected through a conventional test and thus semiconductor circuits which should have been determined as being bad might be shipped or incorporated into apparatuses as being good.
As a new testing method for detecting such defects, a method is being used which sets various states of a semiconductor circuit and then measures static supply (electric) currents flowing through the semiconductor circuit at each of the various states.
The static supply (electric) current or quiescent power supply current, I.sub.DDQ, is an electric current flowing through a CMOS circuit during inputting of a same test vector to the semiconductor circuit being maintained. I.sub.DDQ is very low in a defect-free circuit. Therefore, if I.sub.DDQ of a substantial electric current flows through the semiconductor circuit, it can be determined that the semiconductor circuit contains some defects. Thus, by measuring I.sub.DDQ, whether or not the semiconductor circuit contains some defects can be determined. Such a test is generally referred to as I.sub.DDQ test.
In order to detect all possible defects, it is necessary to set various states of a relevant semiconductor circuit and measure I.sub.DDQ at each state. For the purpose of setting such various states, it is necessary that various test vectors are inputted to the semiconductor circuit and I.sub.DDQ responding to inputting of each test vector is measured.
The test vector or test pattern is a set of signals indicating logic states respectively to be input to particular terminals (input pins, output pins, and both-input-and-output pins) of a semiconductor circuit in parallel at each test cycle.
Whether or not the semiconductor circuit contains any defects is determined from a result as to whether or not a substantial electric current of I.sub.DDQ flows therethrough in response to the inputting of test vector thereto. However, it is possible that the semiconductor circuit includes circuit constructs such that a legal DC current of I.sub.DDQ flows through the semiconductor circuit when a certain test vector is inputted thereto. The legal DC current means a DC electric current which flows through a semiconductor circuit due to predetermined circuit constructs, not due to any defect of the semiconductor circuit. In a such a case of legal-DC-current flowing, a defect-free semiconductor circuit may be determined as containing defects. Such circuit constructs include tri-state busses, floating nodes, certain RAM sense amplifier circuits, pull-up or pull-down resistors on I/O pins, or internal bus-holders.
If a relevant semiconductor circuit includes such circuit constructs, it is necessary to remove, from test vectors to be used in I.sub.DDQ test therefor, test vectors which set states of the semiconductor circuit such that legal DC currents of I.sub.DDQ flow therethrough.
There is a method for detecting similar defects of semiconductor circuits disclosed in Japanese Laid-Open Patent Application No.5-127942. In the method, "0" is set to all internal nodes of an integrated circuit, and also a power supply voltage which is low enough to keep OFF states of all transistors therein. In this state, power supply currents flowing therethrough are measured. However, effectiveness of this method has not been confirmed.
Three methods can be considered for obtaining test vectors for the I.sub.DDQ test, which vectors do not include one which causes any legal DC current to flow through a relevant semiconductor circuit when being inputted thereto.
A first method will now be described. A sample of a relevant CMOS circuit is actually loaded in an IC tester. From among functional-test test patterns or functional-test test vectors for a functional test of the relevant CMOS circuit, various test vectors are selected in a try-and-error manner. The functional-test test vectors are test vectors which are inputted to the relevant semiconductor circuit in a predetermined sequence so as to make sure the semiconductor circuit can perform predetermined dynamic functions. Through the IC tester, each of the thus-selected test vectors is inputted to the sample of the circuit and response thereto is monitored. By repeating such an operation, a test vector can be obtained, which vector sets an internal state of the semiconductor circuit such that any legal DC current of I.sub.DDQ does not flow through the semiconductor circuit can be obtained in the internal state. This method requires considerable labor and time.
A second method will now be described. Test vectors particular for I.sub.DDQ test of a relevant CMOS circuit are created, each of which vectors sets an internal state of the semiconductor circuit such that any legal DC current of I.sub.DDQ does not flow through the semiconductor circuit can be obtained in the internal state. This method also requires considerable labor and time.
A third method will now be described. The above-described functional-test test vectors are automatically searched, in accordance with a certain law, for vectors, each of which set an internal state of a relevant CMOS circuit such that any legal DC current of I.sub.DDQ does not flow through the semiconductor circuit can be obtained in the internal state. For this search, a special apparatus may be used.
For example, Crosscheck Technology, Inc, 2833 Junction Avenue, Suite 100 San Jose, Calif. 95134, United States, provides a software, CurrenTest.TM., which realizes this third method.
As described above, the test vector or test pattern is a set of signals indicating logic states respectively to be input to particular terminals (input pins, output pins, and both-input-and-output pins) of a semiconductor circuit in parallel at each test cycle. The logic states may include not only certain states, "1"/"0" or "H"/"L", but also uncertain states. The uncertain states include "X" states (referred to as Don't Care or Mask). Normally, the logic states "1" and "0" are used for a vector inputting situation while "H" and "L" are used for vector outputting situation.
For example, there is a case where a functional test is performed only on a part of a semiconductor circuit. A test vector to be used for such a case may include non-defined logic states for circuit of inverter INV, when the logic state of "1" (high level) is inputted to an input pin 21, the n-type FET 12 is in an ON state and the p-type FET 11 is in an OFF state. As a result, an output pin 22 is substantially connected to a ground line GND and thus is at "L" state (low level). When the logic state of "0" (low level) is inputted to the input pin 21, the p-type FET 11 is in the ON state and the n-type FET 12 is in the OFF state. As a result, an output pin 22 is substantially connected to a positive voltage line Vcc and thus is at "H" state (high level).
In the circuit of inverter INV, only one of the two FETs 11 and 12 is in the ON state, and therefore no legal DC current flows between the positive voltage line Vcc and the ground line. However, there is a case where a pull-up resistor Ru or a pull-down resistor Rd is connected between the input pin 21 and the positive voltage line Vcc or ground line GND as shown in the figure by a broken line.
A purpose of providing the pull-up or pull-down resistor is to make sure the input level is high or low enough to cause an appropriate one of the two FETs 11 and 12 to be in the ON state and the other one to be in the OFF state. Thus, the operation of the inverter INV may be performed reliably. Specifically, the input pins. The non-defined logic states are those such that the logic states of the test vector, when being inputted to these input pins, do not substantially influence the functions of the relevant part of the semiconductor circuit. These non-defined logic states are the above-mentioned "X" states in the test vector.
Further, logic states for output pins, signals output from which output pins have no relation to the relevant part of the semiconductor circuit may not be defined and thus may be "X" states. Further, logic states for output pins, signals output from which output pins have certain relation to the relevant part of the semiconductor circuit but appearance of the relevant logic state are not stable along the time axis may also be "X" states.
Existence of such "X" states in test vectors may cause problems in a search performed in the above-described third method. Specifically, the above-mentioned certain law used in the third method is such that test vectors fulfill certain conditions are retrieved through the search.
FIG. 1 shows a CMOS circuit INV of an example of a logic element, an inverter. The inverter INV includes p-type and n-type FETs 11 and 12. In the pull-up and pull-down resistors are those effective when a relevant pin of a semiconductor circuit is in an undriven state. The undriven state is also referred to as a floating state or a high-impedance state, and is represented by "Z" in logical simulation.
If there is no provision of either the pull-down or pull-up resistor, when this pin is in the undriven state, an electric potential of this pin may problematically be an intermediate potential, which is neither "1" ("H") nor "0" ("L"). If so, there may be a problematical possibility that both of subsequently coupled p-type FET and n-type FET enter the ON state. This situation is different from a normal situation of this CMOS circuit in which `only one of the p-type FET and n-type FET should be in the ON state.` Accordingly, this situation that both of p-type FET and n-type FET of a subsequent stage enter the ON state is problematic.
In order to prevent such a problematic situation from occurring, the pull-up resistor forcibly causes such an undriven pin to be in the "1" ("H") state and the pull-down resistor forcibly causes such an undriven pin to be in the "0" ("L") state. The provision of a pull-up or pull-down resistor is designed so that, although one of the pull-up or pull-down resistors is provided in the CMOS circuit, when the relevant pin is driven to be either in "1" ("H") or "0" ("L"), that is, either "1" or "0" is input for example, the relevant pin should enter the thus-driven state regardless of the provision of pull-up or pull-down resistor.
However, such pull-up or pull-down resistor may cause a legal DC current to flow through the CMOS circuit. For example, when the "1" state is inputted to the input pin 21 of the inverter INV which has the pull-down resistor Rd provided therein as shown in the figure, a legal DC current flows through the pull-down resistor Rd between the input pin 21 and the ground line GND. Similarly, when the "0" state is inputted to the input pin 21 of the inverter INV which has the pull-up resistor Ru provided therein as shown in the figure, a legal DC current flows through the pull-up resistor Ru between the positive voltage line Vcc and the input pin 21.
In order to prevent such legal DC current from flowing through a CMOS circuit which undergoes I.sub.DDQ test, it is necessary to retrieve test vectors, each of which does not cause such a state that the legal DC current flows through the CMOS circuit as described above with reference to FIG. 1. There is a case where circuit constructs possibly causing a legal DC current of I.sub.DDQ flowing through a relevant CMOS circuit in I.sub.DDQ test are only provision of pull-up or pull-down resistors. In this case, the above-mentioned certain conditions which test vectors to be retrieved should fulfill through the search of the third method are conditions, all of which should be fulfilled by each of the test vectors to be retrieved. If a test vector does not fulfill at least one of these conditions, the test vector causes such a state that the legal DC current flows through a pull-up or pull-down resistor and thus through the CMOS circuit as described above with reference to FIG. 1.
These conditions will now be listed below:
A) The state "1" be inputted to every input pin Pi having the pull-up resistor Ru such as that shown in FIG. 2A (the inverter INV is connected to the pin Pi); PA1 B) The state "1" be inputted to every both-input-and-output pin Pb having the pull-up resistor Ru and in an input mode such as that shown in FIG. 2B (tri-state buffers B are connected to the pin Pb so as to change over input and output modes); PA1 C) The state "L" or "Z" (the high impedance state of the tri-sate logic) be output from every output pin Po having the pull-up resistor Ru such as that shown in FIG. 2C; PA1 D) The state "1" be inputted to every both-input-and-output pin Pb having the pull-up resistor Ru and in the output mode such as that shown in FIG. 2D; PA1 E) The state "L" or "Z" be output from every output pin Po having the pull-down resistor Rd such as that shown in FIG. 2E; PA1 F) The state "L" or "Z" be output from every both-input-and-output pin Pb having the pull-down resistor Rd in the output mode such as that shown in FIG. 2F; PA1 G) The state "0" be inputted to every input pin Pi having the pull-down resistor Rd such as that shown in FIG. 2G; and PA1 H) The state "0" be inputted to every both-input-and-output pin Pb having the pull-down resistor Rd and in the input mode such as that shown in FIG. 2H.
(With regard to circuits shown in FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G and 2H, each circuit is an example of an electric circuit located in a vicinity of external input/output pins in a CMOS LSI circuit. These circuits are only examples and various variants may be considered therefor. In another example, simple buffers may be used instead of the inverters in these circuits. Further, tri-state inverters may be used instead of the tri-state buffers.)
For example, a use of the above-described condition A) will now be described. If at least one input pin Pi having the pull-up resistor Ru is included in a relevant CMOS circuit, the condition A) be considered in the search for adequate test vectors in the third method. If the condition A) is expressed using a negative sentence, the condition A) becomes to a language that `the state "0" not be inputted to the input pin Pi having the pull-up resistor Ru.`
If this input pin Pi has a certain state of "1" or "0" inputted thereto according to every one of the given functional-test test vectors, the search can be performed without causing any problem. A test vector including a state "0" for this input pin Pi cannot be used in I.sub.DDQ test. A test vector including a state "1" for this input pin Pi can be used in I.sub.DDQ test if the other necessary conditions are also fulfilled. Problems may occur when this input pin Pi has the uncertain state "X" inputted thereto according to a test vector.
In the above-described search of the third method, "X" state is treated as a state separate from each of "1" state and "0" state. Therefore, if "X" state is inputted to the input pin Pi having the pull-up resistor Ru according to a test vector, the test vector is determined as not fulfilling the condition A). Therefore, this test vector cannot be used in I.sub.DDQ test.
However, "X" state is a non-defined state but actually is either one of "1", "0", "H", "L", or "Z" state. For example, if "X" state be inputted to an input pin according to a test vector, either one of "1", "0", "H", "L", or "Z" state is inputted to this input pin actually in the IC tester. If "1" state is actually inputted to the input pin having the pull-up register in the IC tester, the condition A) is fulfilled and thus the relevant test vector can actually be used in I.sub.DDQ test.
Thus, according to the third method, determination as to whether or not particular test vectors can be used in I.sub.DDQ test is performed too much strictly. In fact, a test vector which may actually be used is determined as being inadequate as described above. Therefore, if the third method is used to search the given functional-test test vectors for test vectors to be used in I.sub.DDQ test, no adequate test vectors may be retrieved in an extreme case, or an a sufficient number of adequate test vectors for ensuring by I.sub.DDQ test that no defect is contained in the relevant CMOS circuit may not be retrieved.